The subject system and method are generally directed to training a chip select signal to calibrate its timing so that it is synchronized with that of a memory clock of a chip. In particular, the subject method is directed to devices where a chip select signal may be trained such that a pulse of a chip select signal is delayed to align with the positive edge of a dynamic random-access memory (DRAM) clock cycle, using an ability of the DRAM to allow stopping its clock input temporarily around the pulse of the chip select signal.
Digital devices and circuits may have numerous computer chips, such as RAM chips, connected to a single computer bus. When a signal or instruction in the bus is meant for a subset of the chips (usually one), a chip select signal associated with the bus may be used to place that subset of chips in an active state while leaving the remaining chips in an inactive state. The active chip or chips will then receive and respond to the signal or instruction, while the inactive chip or chips will ignore the same signal or instruction, and furthermore will not produce outputs in response.
Some recent designs in devices using DRAM chips require that a chip select signal must be “trained” for use with the DRAM before the associated bus may command high-frequency operations of the DRAM, to ensure efficiency and reduce error. Until the training is achieved, the DRAM is limited to low-frequency operations. This training can include synchronizing signals of the chip select to the cycle of the DRAM's memory clock, to maximize the strength and effectiveness of the signal, and ensure that high-frequency operations may occur without loss or error in the chip select signal.
To assist in this training, some DRAM devices provide methods to stop the memory clock of the DRAM for a selected interval during the training. Such methods can be found in the Low Power Double Data Rate 4 (LPDDR4) Specification, December 2013.
Due to the recent development of this requirement to align the chip select signal with the memory clock, present methods of training the chip select signal are limited and not tailored to the requirement. There is therefore a need for a more effective method of chip select signal training, which will result in improved synchronization and a smaller error rate even at high frequencies.